Recent research has shown that current density-based models for electromigration (EM) lack precision and should be replaced by physics-based hydrostatic stress simulation. While this new approach is widely accepted in the research community, it has not yet found its way into mainstream IC design flows. This paper aims at bringing state-of-the-art stress-based EM modeling into practical IC design by first examining the reasons that prevent the use of stress modeling in today's verification flows, and then proposing solutions that address these obstacles. We present a method for extracting the necessary technology information from standard IC lifetime testing. The stress modeling approach is then used to calculate the lifetime for example structures based on equivalent RC circuits, using common IC design tools. We further verify this approach by implementing reservoirs for extending interconnect lifetime. Additionally, this paper introduces the effect of local temperature variation and its impact on stress evolution. It is shown how equivalent RC circuits can be extended to also model the impact of local temperature on EM. Finally, we implement thermal migration (TM) into the equivalent RC circuits. © 2025 The Authors

This work presents an analytical approach for analyzing electromigration (EM) in modern technologies that use copper dual damascene (Cu DD) interconnects. In these technologies, due to design rule and methodology constraints, wires are typically laid out unidirectionally in each metal layer; since EM in Cu DD interconnects do not cross layer boundaries, the problem reduces to one of analyzing EM in multisegment interconnect lines. In contrast with traditional empirical methodologies, our approach is based on physics-based modeling, directly solving the differential equations that model EM-induced stress. This article places a focus on interconnect lines, for reasons described above, and introduces the new concept of boundary reflections of stress flux that ascribes a physical (wave-like) analogy to the transient stress behavior in a finite multisegment line. This framework is used to derive analytical expressions of transient EM stress for lines with any number of segments, which can also be tailored to include the appropriate number of terms for any desired level of accuracy. The approach is applied to both the nucleation phase and the postvoiding phase on large power grid benchmarks. These experiments demonstrate excellent accuracy as compared to accurate numerical solution, as well as linear complexity with the number of segments for evaluating stress at a specified point and time. © 2025 Copyright held by the owner/author(s). Publication rights licensed to ACM.

Power delivery is a significant bottleneck in 2.5D heterogeneously integrated (HI) systems. A key part of the solution lies in the use of voltage regulators that distribute power to the chiplets with low transmission losses, thus ensuring supply levels that meet design specifications. Early HI systems have used manual approaches for placement, but as systems grow more complex and employ heterogeneous chiplets with nonuniform power distributions, the solution becomes nontrivial, and automation is essential. This paper addresses the problem of voltage regulator selection and placement for early-stage power planning in HI systems under DC estimates of chiplet loads. It demonstrates an HI technology using an active silicon interposer with embedded switched-capacitor voltage regulators (SCVRs). The problem is formulated as a 0-1 mixed integer linear program (MILP) and determines the optimal number, location, and types of SCVRs. A key part of the solution is using a macromodeling approach to control the size of the MILP. Experimental results across four test cases - covering both homogeneous and heterogeneous chiplet configurations - demonstrate that the method can efficiently find optimal solutions. The tested scenarios span a wide range of power densities, from 0.8 to 4.0W/mm2, and include total load currents ranging from 800A to 1200A. In all cases, the method achieves high accuracy (average error below 1.7%) and completes the optimization within practical runtimes, ranging from 18.8 to 46.1 minutes. © 2025 IEEE.