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全球科研项目数据库2026版

SHF:Small:Enhancing Performance and Reliability in On-Chip Power Distribution Networks

项目来源

美国国家科学基金(NSF)

项目主持人

Sachin S Sapatnekar

项目受资助机构

UNIVERSITY OF MINNESOTA TWIN CITIES

财政年度

2025,2024

立项时间

未公开

项目编号

2437795

研究期限

未知 / 未知

项目级别

国家级

受资助金额

1200000.00美元

学科

未公开

学科代码

未公开

基金类别

Standard Grant

关键词

Software&Hardware Foundation ; SMALL PROJECT ; DES AUTO FOR MICRO&NANO SYST

参与者

未公开

参与机构

REGENTS OF THE UNIVERSITY OF MINNESOTA

项目标书摘要：Today’s world is increasingly driven by advanced electronic integrated circuits,or chips,which power artificial intelligence(AI),infrastructure,mobile communications,scientific computation,and consumer electronics.The computations in a chip are facilitated by supply voltages that are distributed to the computational elements through power distribution networks(PDNs).These PDNs consist of structures that carry large currents through lossy filamentous wires,which may be inadequate for ensuring robust voltage levels at the computational elements.These effects can potentially lead to incorrect computations and unacceptable errors.Moreover,high currents can cause accelerated aging in the PDN due to phenomena such as electromigration(EM)that can result in chip failure.Developing optimization strategies that ensure supply voltage integrity and PDN reliability is therefore critical.The task is further complicated with the challenges associated with emerging methods for building advanced integrated circuits,including new wire and transistor structures,and elevated on-chip currents and temperatures that degrade performance and reliability.Therefore,the development of PDN design techniques is vital for enabling the next generation of chips that drive computation from the datacenter to the edge.This project aims to address the challenges of optimizing voltage drop and EM in PDNs,while ensuring minimal utilization of the limited available on-chip wiring resources.For the problem of voltage drop,the work will address today’s widely used front-side interconnects as well as newer backside interconnect technologies.Degradations in supply voltages can also cause circuit delays to deteriorate:the interplay of PDN optimization on circuit timing in digital circuits will be addressed in this project through new approaches that break down the barrier between PDN design and timing optimization,performing integrated optimizations that benefit both PDN resource usage and logic circuit metrics.To address EM,this research will advance the use of physics-based approaches that predict chip lifetimes by directly modeling EM-induced stress in interconnects.New methods will be developed based on a stress-electrical duality that maps accurate physics-based stress analysis to methods for analyzing resistor-capacitor(RC)networks and transmission lines.An educational component of the project aims to attract fresh talent to advance the mission of workforce development in the field of electronic design automation.Specific efforts will target students at the K-12,undergraduate,and graduate levels,and intend to attract women and other underrepresented minority groups.Outreach activities will be centered around artificial intelligence and semiconductor technologies,and will be supplemented by curriculum development efforts.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

人员信息

Sachin S Sapatnekar(Principal Investigator)：sachin@umn.edu；

机构信息

【University of Minnesota-Twin Cities(Performance Institution)】StreetAddress：200 Union Street SE,Minneapolis,Minnesota,United States/ZipCode：554550160；【REGENTS OF THE UNIVERSITY OF MINNESOTA】StreetAddress：2221 UNIVERSITY AVE SE STE 100,MINNEAPOLIS,Minnesota,United States/PhoneNumber：6126245599/ZipCode：554143074；

项目主管部门

Directorate for Computer and Information Science and Engineering(CSE)-Division of Computing and Communication Foundations(CCF)

项目官员

Sankar Basu(Email：sabasu@nsf.gov；Phone：7032927843)

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  • 1.Temperature-aware stress-based migration modeling in IC design: Moving from theory to practice

    • 关键词：
    • Equivalent circuits;Integrated circuit design;Integrated circuit interconnects;Stresses;Timing circuits;'current;'spice';Equivalent RC circuit;Interconnect reliability;Local temperature;Migration modelling;Recent researches;Stress models;Temperature aware;Thermal migration
    • Rothe, Susann;Lienig, Jens;Sapatnekar, Sachin S.
    • 《AEU - International Journal of Electronics and Communications》
    • 2025年
    • 200卷
    • 期刊

    Recent research has shown that current density-based models for electromigration (EM) lack precision and should be replaced by physics-based hydrostatic stress simulation. While this new approach is widely accepted in the research community, it has not yet found its way into mainstream IC design flows. This paper aims at bringing state-of-the-art stress-based EM modeling into practical IC design by first examining the reasons that prevent the use of stress modeling in today's verification flows, and then proposing solutions that address these obstacles. We present a method for extracting the necessary technology information from standard IC lifetime testing. The stress modeling approach is then used to calculate the lifetime for example structures based on equivalent RC circuits, using common IC design tools. We further verify this approach by implementing reservoirs for extending interconnect lifetime. Additionally, this paper introduces the effect of local temperature variation and its impact on stress evolution. It is shown how equivalent RC circuits can be extended to also model the impact of local temperature on EM. Finally, we implement thermal migration (TM) into the equivalent RC circuits. © 2025 The Authors

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  • 2.An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model

    • 关键词：
    • Differential equations;Economic and social effects;Integrated circuit interconnects;Power quality;Analytical approach;Damascene Cu;Design Methodology;Dual damascene;Interconnect;Interconnect lines;Modern technologies;Multi-segment;Stress wave;Wave modelling
    • Shohel, Mohammad Abdullah Al;Chhabria, Vidya A.;Evmorfopoulos, Nestor;Sapatnekar, Sachin S.
    • 《ACM Transactions on Design Automation of Electronic Systems》
    • 2025年
    • 30卷
    • 4期
    • 期刊

    This work presents an analytical approach for analyzing electromigration (EM) in modern technologies that use copper dual damascene (Cu DD) interconnects. In these technologies, due to design rule and methodology constraints, wires are typically laid out unidirectionally in each metal layer; since EM in Cu DD interconnects do not cross layer boundaries, the problem reduces to one of analyzing EM in multisegment interconnect lines. In contrast with traditional empirical methodologies, our approach is based on physics-based modeling, directly solving the differential equations that model EM-induced stress. This article places a focus on interconnect lines, for reasons described above, and introduces the new concept of boundary reflections of stress flux that ascribes a physical (wave-like) analogy to the transient stress behavior in a finite multisegment line. This framework is used to derive analytical expressions of transient EM stress for lines with any number of segments, which can also be tailored to include the appropriate number of terms for any desired level of accuracy. The approach is applied to both the nucleation phase and the postvoiding phase on large power grid benchmarks. These experiments demonstrate excellent accuracy as compared to accurate numerical solution, as well as linear complexity with the number of segments for evaluating stress at a specified point and time. © 2025 Copyright held by the owner/author(s). Publication rights licensed to ACM.

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