As deep neural networks increase their demand for computing power, traditional electronic architectures are experiencing bottlenecks in terms of computational speed and energy consumption. Optical computing, with its high scalability, high parallelism, fast operation, and low power consumption, is increasingly showing its advantages. To this end, we constructed an optical computing architecture based on an arrayed waveguide grating router (AWGR) optical convolution unit (OCU) to accelerate convolutional neural networks. The wavelength routing characteristics of the AWGR enable convolution operations to be mapped to the optical domain, achieving a linear relationship between input size and device number. We used the ResNet-50 neural network for demonstration experiments, trained and fine-tuned using the CIFAR-10 dataset. In this hybrid optical-electrical architecture, only the first-layer convolution operations were accelerated, while the remaining operations were performed in the electronic domain. Results show that, driven by a 2GHz FPGA, a single-frame convolution takes only approximately 0.3ms, resulting in a system processing capacity of over 3320 frames per second for color images and a theoretical peak computing power of 65.536 TOPS. The research results verify the potential of AWGR-OCU in efficient parallel computing and provide a feasible idea for the design of future large-scale optical acceleration AI computing chips. © 2025 SPIE.

We propose a calibration-free MZI and demonstrate its large-scale scalability with a 64 ×64 MZI. This robust methodology for suppressing random phase imbalance can be generalized for any essential phase-sensitive photonic integrated devices. © Optica Publishing Group 2025.

We propose and simulate a frequency-angle encoded frequency-modulated continuous wave (FMCW) lidar system that achieves high-fidelity 4D (x, y, z, and velocity) point cloud imaging via synchronized spatio-spectral modulation. By incorporating a programmable frequency-shifted FMCW transmitter with a focal plane switch array (FPSA), the system enables deterministic angular coordinate encoding within the optical frequency domain. At the receiver end, coherent detection enables direct extraction of scanning angle information from echo signal frequencies, along with target distance and velocity measurements. Compared with conventional FMCW systems, this innovation supports bistatic transmitter-receiver configurations and asynchronous operation, significantly enhancing system flexibility, signal-to-noise ratio, and detection speed. The methodology offers novel sensing solutions for autonomous driving and intelligent robotics applications. © 2025 SPIE.

Reconfigurable silicon optical signal processors using interferometer meshes are essential in optical interconnection and optical computing systems. However, due to random phase errors in the tuning elements, most of the pervious demonstrations either require hundreds of self-configuration iterations or calibration of all the tuning elements. Here, we propose and demonstrate a calibration-free silicon optical signal processor based on 5× 5 interferometer mesh using low-phase-error Mach-Zehnder interferometer (MZI). The proposed processor can be tuned easily to achieve various functions, including multi-channel optical switch and matrix multiplications. Our work paves the way towards large-scale calibration-free silicon photonic MZI-based processors. © 2023 IEEE.

We present a 0.4-nm channel spacing silicon arrayed-waveguide grating with Euler-bend-assisted broadened arrayed waveguides and shallowly-etched transition regions. For the present AWG, the excess loss is 0.65-3.11 dB and the crosstalk is below-18 dB. © 2023 IEEE.

We proposed a 32-channel 50G AWG as the core device to implement the on-chip optical reservoir computing. With appropriate iterative mode and output-level training strategy, the chip has achieved good results in predicting Macky-Glass series. For sequences of 1000 length, this type of optical reservoir calculation can obtain an absolute error of about 0.02 and a relative error of 0.018. © 2023 IEEE.