项目来源

台湾省政府科研基金(GRB)

项目主持人

陈胜利

项目受资助机构

台湾省联合大学电子工程学系

立项年度

2017

立项时间

未公开

项目编号

MOST106-2221-E239-018

研究期限

未知 / 未知

项目级别

省级

受资助金额

825.00千元台币

学科

电子电机工程

学科代码

未公开

基金类别

技术发展/学术补助

体极区 ; 静电放电(ESD) ; 内镶式 SCR ; 保持电压(Vh) ; 人体静电放电模型 ; 过电压破坏(EOS) ; 横向扩散金氧半电晶体 ; 电力转换 ; 二次崩溃电流(It2) ; 传输线脉冲量测仪 ; 触发导通电压值(Vt1) ; 超高压 ; Bulk Region ; Electrostatic Discharge(ESD) ; Embedded SCR ; Holding Voltage(Vh) ; Human-Body Model ; Electrical over stress(EOS) ; Lateral double-diffused MOS

参与者

陈勋祥；陈宏伟

参与机构

未公开

项目标书摘要：超高压(Ultra High-Voltage)横向扩散金氧半功率电晶体(Lateral-diffused MOSFET;LDMOS)经常使用在DC/AC 或AC/DC 电力转换积体电路中，因此超高压LDMOS 电晶体元件在电能转换模组(例如太阳能发电系统)上扮演相当重要角色。本计划接续前些年中压(40V~60V)电力组件的开发经验，为新探讨可靠性能力相当差的超高压300V LDMOS 组件，如何利用体/源极及汲极内镶SCR 工程技术提升其抗静电放电防护可靠度能力。由於电压更高的超高压LDMOS 电晶体其抗ESD 的能力比起一般低电压制程之积体电路更差。又因为使用环境关系,UHV LDMOS 组件必须拥有高静电防护能力，使其具有较佳的可靠性特性。在电力转换技术积体电路中，高可靠度的超高压LDMOS 元件应该具有一个较低的触发导通电压值(Vt1)、高的等效抗静电放电It2 值及较高的保持电压(Vh)能力值。针对电力转换超高压 N 型通道LDMOS(nLDMOS)电晶体，若元件结构未最佳化处理前它有几个严重缺点，包括nLDMOS 电晶体Vt1 太高、Vh 又太低且在多指状结构里不能完全导通而导致每单位面积的静电放电能力太低。反观SCR 元件也常因它每单位面积有非常强大的静电放电能力而被使用在高压应用里；但它也有一些缺点，包括Vh 太低等。因此我们试想将这两个元件内镶结合在一起，利用在UHV nLDMOS 的汲极端植入P+来形成nLDMOS-内镶式SCR 结构。因此本年度研究的第一部分将探讨超高压 nLDMOS 汲极端植入内镶式SCR 的不同布局方式，对静电放电防护能力/EOS 免疫力的提升及影响是多少?第二部分则为在超高压 LDMOS 组件的体/源极端(bulk/source)施以调变工程，也就是说在体极端均匀及非均匀插入Field-oxide device(FOD)形成离散结构，透过调整FOD 参数探讨其数值对抗ESD 能力的影响。希望藉由各种体/源极端离散分布型式，增加 LDMOS 寄生BJT 的RBulk 串联电阻，提升静电放电It2 能力值，最终对其分析对静电放电防护能力/EOS 免疫力的提升及影响是多少?本计划也将利用布局设计调变的超高压 nLDMOS-内镶式SCR 结构及nLDMOS 体/源极结构参数值，再利用EDA 软体加以模拟验证。对於此实际下线後的超高压LDMOS 及LDMOS-内镶式SCR 的抗静电放电防护能力/EOS 免疫力分析，我们将使用传输线脉冲测量仪、HBM 测试来验证之，最後建立出可供电力转换IC 使用的超高压LDMOS+内镶式SCR 及nLDMOS+体极端P+离散分布型式如何达到高静电防护能力/EOS 免疫力的布局调变模型。

Application Abstract: An UHV LDMOS is popular used in the AC/DC or DC/AC power inverter integrated circuits.Then,it is acted as an important roles in the solar-cell power electronic module.Based on our previous MV(40V~60V)experiences,in this current year of this project,we will focus on the high ESD robustness/high EOS immunity capabilities of a new type UHV 300V LDMOS by the drain-side embedded an SCR and bulk/source engineering.In the power converter technology,a circuit structure in the high efficiency pad should have lower triggering voltage(Vt1),higher secondary breakdown current(It2)and higher holding voltage(Vh).Therefore,this UHV power nLDMOS unit will be able to guarantee with good ESD protection robustness and good electrical over stress(latch-up)immunity.For an UHV nLDMOS in the power inverter unit,it has several obvious disadvantages,including Vt1 is too high,Vh is too low,the device in a multi-finger structure can’t completely turn on,resulting in per unit area ESD robustness is very poor.Meanwhile,an SCR has a very strong ESD capacity per unit area,but it also has some weak points,including the Vh is too low.Therefore,it is brightening an idea in this project to integrate these two components that the drain-side of an nLDMOS is implanted by a P+structure to form an UHV LDMOS-embedded SCR structure.Therefore,the first part of this project will aim to verify the influences and impacts of an UHV nLDMOS-embedded SCR with different P+layout manners in the drain side to the anti-ESD robustness and EOS immunity levels.The second part of this planning project is a new bulk/source engineering of the UHV 300V nLDMOS.The subject is at the bulk-end in which some even and non-even discontinuous field-oxide devices(FODs)are applied to the bulk region of UHV nLDMOS devices.We aimed to increase the RBulk value of a parasitic BJT of an UHV LDMOS in the bulk/source side with an invariant device cell area size.Therefore,we will aim to verify the influences and impacts of an UHV nLDMOS with different bulk/source layout manners to the anti-ESD robustness and EOS immunity levels.Therefore,a high reliability of an UHV 300V nLDMOS-embedded SCR devices and bulk/source structures of an UHV 300V nLDMOS will be designed and simulated by the EDA simulators such as TSUPREM 4 and 3-D Davinci.For the measurement and analysis of these new designed structures,beside HBM ESD testing,the recently developed transmission-line pulse(TLP)system in our Lab.for ESD/LU testing will be used to evaluated.And,high anti-ESD robustness/EOS immunity capabilities of the UHV nLDMOS-embedded SCRs and nLDMOS-bulk/source engineering can be achieved and its optimized layout model and correlation model will be established in this project,which can be applied to the AC/DC or DC/AC power inverter circuit design with a high reliability robustness.

项目受资助省

台湾省